Semiconductors — Top 20 Questions

Zener breakdown: in heavily doped junctions with narrow depletion layers. Strong electric field in narrow depletion layer causes valence electrons to tunnel → breakdown at low reverse voltage (~5V). Avalanche breakdown occurs in lightly doped junctions at higher voltage.

In semiconductors, increasing temperature generates more electron-hole pairs (thermal excitation across band gap). More carriers → conductivity increases → resistance decreases. This is the opposite of metals (where resistance increases with temperature).

\(R = (V_{battery} - V_D)/I_{max} = (1.5-0.5)/(10\times10^{-3}) = 1.0/0.01 = \mathbf{100\Omega}\).

\(E = V/d = 0.6/(6\times10^{-6}) = 10^5\text{ N/C} = \mathbf{1\times10^5\text{ N/C}}\).

\(E = hc/\lambda = 1240\text{ eV·nm}/400\text{ nm} = 3.1\text{ eV} \approx \mathbf{3\text{ eV}}\).

p-type semiconductor is formed by doping with trivalent impurities (B, Al, Ga). Each dopant atom creates a hole → holes are majority carriers, electrons are minority carriers.

NAND gate: output = NOT(A·B). For (1,1): A·B = 1, NOT(1) = 0. NAND output is 0 only when both inputs are 1; otherwise output is 1.

\(I_C = \beta I_B = 100\times50\times10^{-6} = 5\times10^{-3}\text{ A} = \mathbf{5\text{ mA}}\).

Depletion region forms by diffusion of majority carriers: electrons from n-side diffuse to p-side, holes from p-side diffuse to n-side. They recombine, leaving behind fixed ionized donor/acceptor atoms → built-in electric field.

Forward bias: p connected to +ve, n to -ve terminal. Barrier potential decreases → majority carriers flow across junction → large current. In reverse bias: depletion region widens, only tiny minority carrier current flows.

OR gate: output = A+B (logical OR). For A=1, B=0: output \(= 1+0 = \mathbf{1}\). OR output is 0 only when both inputs are 0.

n-type: doped with pentavalent (Group 15) elements: Phosphorus (P), Arsenic (As), Antimony (Sb). Extra electron becomes majority carrier. p-type: trivalent (Group 13): Boron, Aluminium, Gallium.

Zener diode in reverse bias breakdown maintains constant voltage across it. Used as voltage regulator — output voltage remains constant despite variations in input or load. Connected in parallel with load.

Half-wave rectifier passes only alternate half cycles → output frequency = same as input = 50 Hz. Full-wave rectifier passes both half cycles → output frequency = 100 Hz (double the input).

NAND gate: \(Y = \overline{AB} = \overline{A\cdot B}\). De Morgan's theorem: \(\overline{AB} = \bar{A}+\bar{B}\). NOR gate: \(Y = \overline{A+B}\). \(\mathbf{\overline{AB}}\).

At 0 K, all valence electrons are in valence band, conduction band is completely empty. No thermal energy to excite electrons across band gap. Intrinsic semiconductor behaves as perfect insulator at 0 K.

Voltage gain \(= \beta R_C/R_i = 50\times2000/500 = 50\times4 = \mathbf{200}\).

Silicon band gap \(\approx \mathbf{1.1\text{ eV}}\) at room temperature. Germanium: 0.67 eV. Diamond: 5.4 eV. GaN: 3.4 eV. Band gap of Si makes it ideal for room temperature semiconductor devices.

NOR gate (like NAND) is a universal gate because any Boolean function can be realized using only NOR gates. NOT: NOR with both inputs same. AND: three NORs. OR: two NORs. This simplifies IC manufacturing.

Bridge rectifier uses 4 diodes arranged in a bridge configuration. During positive half cycle: 2 diodes conduct. During negative half cycle: other 2 diodes conduct. Both half cycles appear at output with same polarity. No centre-tapped transformer needed.